1. Field of the Invention
The present invention relates to a thin film transistor, and more particularly, to a method of manufacturing the same. Also, the present invention relates to an active matrix display device having improved reliability and a manufacturing method is thereof.
2. Description of Related Art
A cathode ray tube (CRT) is widely employed as display devices for use in televisions, measuring instruments, information terminals, etc. However, the CTR has disadvantages that it cannot satisfy trends toward miniaturization and lightweight of electronic appliances.
Due to such shortcomings of the CRT, flat panel display devices, which are lightweight and small-sized, is being watched with keen interest.
FIG. 1 is a cross-sectional view illustrating a TFT array substrate of an active matrix flat panel display device according to a conventional art. A process of manufacturing the conventional TFT array substrate is described below.
First, a buffer layer 11 is formed on a transparent substrate 10. The buffer layer 11 is an oxide layer, and the substrate is a transparent glass substrate or a transparent plastic substrate. A polycrystalline silicon layer is deposited on the buffer layer 11 and then patterned to form a semiconductor layer 12.
Then, a first insulating layer 13 is deposited over the whole surface of the substrate 10 and covers the semiconductor layer 12. The first insulating layer 13 serves as a gate insulating layer. A first metal layer is deposited on the first insulating layer 13 and then patterned to form a gate electrode 14 over the semiconductor layer 12. A high-density impurity, for example, an n-type or a p-type high-density impurity is ion-implanted into the semiconductor layer 12 to form high-density source and drain regions 15-1 and 15-2 on both end portions of the semiconductor layer 12.
Thereafter, a second insulating layer 16 is deposited over the whole surface of the substrate 10 and then patterned to form first and second contact holes 17-1 and 17-2. The first contact hole 17-1 is formed at a location corresponding to a portion of the source region 15-1, and the second contact hole 17-2 is formed at a location corresponding to a portion of the drain region 15-2. The second insulating layer 16 serves as an inter insulating layer.
Subsequently, a second metal layer is deposited on the inter insulating layer 16 and then patterned to form source and drain electrodes 18-1 and 18-2. The source and drain electrodes 18-1 and 18-2 contact the source and drain regions 15-1 and 15-2 through the first and second contact holes 17-1 and 17-2, respectively.
Next, a passivation layer 19 is formed over the whole surface of the substrate 10 and covers the source and drain electrodes 18-1 and 18-2. The passivation layer 19 includes a via hole 20 at a location corresponding to a portion of either of the source and drain electrodes 18-1 and 18-2. In FIG. 1, the via hole 20 is formed on a portion of the drain electrode 18-2.
A transparent conductive material layer is deposited and then patterned to form a pixel electrode 21. The pixel electrode 21 contacts the drain electrode 18-2 through the via hole 20.
Finally, a planarization layer 22 is deposited and then patterned to form an opening portion 23. The opening portion 23 exposes a portion of the pixel electrode 21. Therefore, the TFT array substrate of the flat panel display device is completed.
The source and drain electrodes 18-1 and 18-2 are electrodes to which electrical signals are applied and are made of a low resistive metal to prevent a signal delay. The pixel electrode 21 is made of a low resistive, high transmitting material, for example, a transparent conductive material such as indium tin oxide (ITO).
Therefore, when the source and drain electrodes and the pixel electrode are made of metal, they are low in specific resistance but low in transmittance. Alternatively, when the source and drain electrodes and the pixel electrode are made of ITO, they are high in transmittance but high in specific resistance in comparison to metal. Neither of metal and ITO cannot satisfy requirements of the source and drain electrodes and the pixel electrode.
Therefore, in conventional manufacturing process of the TFT array substrate of the flat panel display device, the source and drain electrodes are made of metal, and the pixel electrode is made of ITO. As a result, two mask processes are required to form the source and drain electrodes and the pixel electrode. In addition, a process is additionally required that forms the contact hole in the passivation layer to contact one of the source and drain electrodes and the pixel electrode.
As described above, the conventional process of manufacturing the TFT array substrate of the flat panel display device is very complicated. Therefore, manufacturing yield is low, and production cost is high.
Also, the TFT array substrate of the flat panel display device has a problem in that a contact resistance between the source and drain regions and the source and drain electrodes is very large sufficiently to degrade electric characteristics thereof.